The present invention relates generally to junction field-effect transistor (JFET) devices and more particularly to a method for fabricating JFET devices and the devices produced by the method.
The junction field-effect transistor, also referred to as the unipolar transistor, is known in the art. Such a device was first proposed by William Shockley in an article entitled "A Unipolar Field Effect Transistor" published in the Proceedings of the IRE 40, p. 1365 (1952). The first experimental demonstration of the JFET was reported by G. C. Dacey and I. M. Ross in an article entitled "Field Effect Transistor" published in the Bell System Technical Journal 34, p. 1149 (1955). Today the JFET is in widespread use, particularly as discrete devices for high power applications.
Electrical current in a JFET is transported entirely by majority carriers of a single polarity (i.e., electrons or holes). Hence the JFET is also known as the unipolar transistor. Current flow through the JFET is largely controlled by varying the width of a depletion layer associated with a P-N junction formed between a gate zone and a conducting channel of the device, the cross-sectional area of the conducting channel being altered by the variation in the width of the depletion layer.
In recent times, JFETs are most commonly fabricated using planar silicon technology. A typical JFET structure 10 fabricated with such technology is illustrated in FIG. 1. Referring now to FIG. 1, a relatively low impurity concentration N-type silicon layer 1 is epitaxially grown on a relatively high impurity concentration P-type (P+) silicon substrate 2. A relatively high impurity concentration P-type gate zone 3 is then formed by a masked diffusion of P-type impurities from the exposed surface 13 of the epitaxial layer 1. The gate zone is interposed between a source region 4 and a drain region 5 of the N-type layer 1. Finally, gate, source and drain contacts are formed by means of strip-like metallic layers 6, 7 and 8 deposited on the surfaces of the gate zone 3, the source region 4 and the drain region 5, respectively. In order to insure good electrical contact to the relatively low impurity concentration source and drain regions it is generally necessary to increase the surface impurity concentration of those regions by an additional masked diffusion of N-type impurities into the top surface beneath the source and drain contacts 7 and 8. Such a contact diffusion step is not illustrated in FIG. 1.
When appropriate bias voltages are applied to the gate, source and drain contacts, 6, 7 and 8 and to the substrate 2, current flows from the source region 4 to the drain region 5 through an N-type region 9 bounded by the depletion layers 11 and 12 of the P-N junctions between the gate zone 3 and the N-type region 9 and between the substrate 2 and the N-type region 9, respectively. The portion of the N-type region 9 between the depletion layers 11 and 12 is commonly referred to as the channel of the device. The resistance of the channel is proportional to its length L and inversely proportional to its width W and its thickness. The thickness of the channel may be expressed as the thickness d of the N-type region 9 less the widths w.sub.1 and w.sub.2 of the depletion layers 11 and 12, respectively. Therefore, the channel resistance of the device may be varied by altering the depletion layer widths w.sub.1 and w.sub.2 through appropriate changes in the voltages applied to the device, and the minimum channel resistance of the JFET is proportional to the channel width W and the gate zone-to-substrate distance d and inversely proportional to the channel length L.
Certain applications for the JFET require that the device be capable of carrying relatively high currents. For such applications it is necessary to fabricate the JFET to have a relatively low minimum channel resistance. In fabricating JFET devices for high current applications, conventional methods of fabrications which use an epitaxial layer have the problem in that owing to the impracticality of growing thick epitaxial layers, the devices fabricated by such methods generally have a relatively small gate zone-to-substrate distance d. Consequently, in order to fabricate a JFET having a low minimum channel resistance using conventional methods, it is necessary to provide the device with a relatively large channel width W. In so doing, the lateral dimensions of the JFET device must be made relatively large, and the number of devices that can be formed on a substrate wafer is accordingly reduced. For that reason, high current JFETS are costly to manufacture using conventional fabrication methods.
In this regard it is also noted that in the JFET device fabricated by conventional methods, most of the device structure in the vertical direction is inactive, since the active device regions, i.e., gate zone 3, the source and drain regions 4 and 5 and the channel, are all confined to the epitaxial layer 1 which has a thickness t many times smaller than the thickness T of the substrate 2.
Therefore, a need clearly exists for a method for fabricating high current JFET devices which are more compact and less costly to manufacture. Furthermore, a need exists for a fabrication method which provides a JFET structure in which the active device regions extend through substantially the entire thickness of the substrate.